AMD turns to chiplets as Moore’s Law slows



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Mark Papermaster is CTO and Executive Vice President at AMD.

Moore's Law has been driving the pace of innovation in the semiconductor industry for more than five decades – and is driving the evolution of the computer lab from early desktops and laptops to cloud computing and the Internet of Things today.

Every 18 to 24 months, twice the number of transistors per unit area was pinned into our silicon chips. This has helped reduce costs and improve performance and power consumption in successive generations of microchips. As microchips became increasingly compact, thinner computing factors such as mobile phones, tablets, and ultra-thin laptops could be used.

Moore's law is slowing down and it's harder than ever to make improvements every 18 to 24 months. Reducing dimensions is a big challenge and it takes longer to discover new manufacturing technologies that allow silicon to be continuously miniaturized.

From the point of view of the industry, this stagnation is a genuine innovation boost. The processor design approach must balance the gaps to achieve product level improvements at the pace of traditional Moore's Law.

The chiplet approach

We need a new processor design approach to extend the historical gains of the last decades to the decades to come. An established solution is the chiplet approach, where you create a single processor package from multiple different chiplets and connect them using a die-to-die connection scheme. With chipsets, I / O, memory, and processor cores can be flexibly assembled faster and at lower cost. Many industry players are moving to this modular design approach.

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If the design approach provides a modular architecture, parts of the design that are difficult to manufacture may be broken down into small chip sizes. With a small chip, we get a higher yield and a higher number of chips per wafer, which helps further reduce manufacturing costs and increase production efficiency.

There are several important factors that make a chip architecture compelling:

  • The product has a big appetite for throughput, so the cost of having several smaller chips in the package is significantly lower than traditional monolithic designs.
  • There must be an essential component of the analog / mixed-signal IP that does not benefit from the cutting-edge technology.
  • The product should benefit from the flexibility afforded by varying the number of chips across the product line. For example, at AMD we sell one, two and four die versions of our "Zen" architecture in the AMD Ryzen ™, Ryzen ™ Threadripper ™ and EPYC processors.

The 7nm jump

7nm is an important step in the chiplet strategy. Not only are small 7nm CPU chips efficient and cost effective, they also enable unprecedented cost and performance configurability of the product, varying in number depending on market segment requirements.

The other obvious benefit is that by combining all of the storage and I / O interfaces on a monolithic I / O chip, businesses can improve performance by reducing average memory and I / O latencies. In computer systems, such as servers, where performance and performance are completely dominated by the CPU cores and caches, it is crucial to take advantage of the 7nm advantages of this IP.

The resulting benefits to the end user include improved performance, lower power consumption, improved memory latency, and a higher clock speed.

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The chiplet approach is the new direction for the semiconductor industry. The advances in performance, efficiency and architectural flexibility based on this modular strategy will extend Moore's legal benefits in the future.

In addition, the use of the chiplet approach will enable new innovations for the semiconductor industry to meet the demand for ever-increasing processing power and specialized computing tasks in areas such as AI, real-time graphics rendering and simulation, and supercomputing.

Mark Papermaster is CTO and Executive Vice President at AMD,

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